The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
For example, traditional photolithography alone can no longer meet the requirements for critical dimension (CD) and pattern density in advanced process nodes, such as 20 nanometer (nm) or smaller. Frequently, a mandrel-spacer technique is used for doubling the exposed pattern in advanced photolithography. A typical mandrel-spacer technique forms mandrel patterns in a first exposure, and forms spacer features on sidewalls of the mandrel patterns. Subsequently, it removes the mandrel patterns and uses the spacer features as an etch mask for forming a final pattern. This technique effectively reduces the pitch of the final pattern by half compared with the first exposed pattern.
However, it is challenging for typical mandrel-spacer techniques to produce both uniform pitches and uniform CDs simultaneously in the final pattern.